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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>MOVA (tile to vector, single)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">MOVA (tile to vector, single)</h2><p>Move ZA tile slice to vector register</p>
      <p class="aml">The instruction operates on individual horizontal or vertical slices within a named ZA tile of the specified element size. The slice number within the tile is selected by the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is in the range 0 to the number of elements in a 128-bit vector segment minus 1.</p>
      <p class="aml">Inactive elements in the destination vector remain unmodified.</p>
    <p class="desc">This instruction is used by the alias <a href="mov_mova_z_p_rza.html" title="Move ZA tile slice to vector register">MOV (tile to vector, single)</a>.</p>
    <p class="desc">
      It has encodings from 5 classes:
      <a href="#iclass_per_byte">8-bit</a>
      , 
      <a href="#iclass_per_halfword">16-bit</a>
      , 
      <a href="#iclass_per_word">32-bit</a>
      , 
      <a href="#iclass_per_doubleword">64-bit</a>
       and 
      <a href="#iclass_per_quadword">128-bit</a>
    </p>
    <h3 class="classheading"><a id="iclass_per_byte"/>8-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td colspan="3" class="lr">Pg</td><td class="lr">0</td><td colspan="4" class="lr">off4</td><td colspan="5" class="lr">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="5"/><td class="droppedname">Q</td><td/><td colspan="2"/><td colspan="3"/><td/><td colspan="4"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_z_p_rza_b"/><p class="asm-code">MOVA    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.B, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>/M, ZA0<a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.B[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offs" title="Slice index offset [0-15] (field &quot;off4&quot;)">&lt;offs&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
integer n = 0;
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off4);
constant integer esize = 8;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_halfword"/>16-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td colspan="3" class="lr">Pg</td><td class="lr">0</td><td class="lr">ZAn</td><td colspan="3" class="lr">off3</td><td colspan="5" class="lr">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="5"/><td class="droppedname">Q</td><td/><td colspan="2"/><td colspan="3"/><td/><td/><td colspan="3"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_z_p_rza_h"/><p class="asm-code">MOVA    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.H, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>/M, <a href="#sa_zan_1" title="ZA tile ZA0-ZA1 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.H[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offs_2" title="Slice index offset [0-7] (field &quot;off3&quot;)">&lt;offs&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off3);
constant integer esize = 16;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_word"/>32-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td colspan="3" class="lr">Pg</td><td class="lr">0</td><td colspan="2" class="lr">ZAn</td><td colspan="2" class="lr">off2</td><td colspan="5" class="lr">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="5"/><td class="droppedname">Q</td><td/><td colspan="2"/><td colspan="3"/><td/><td colspan="2"/><td colspan="2"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_z_p_rza_w"/><p class="asm-code">MOVA    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.S, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>/M, <a href="#sa_zan_3" title="ZA tile ZA0-ZA3 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.S[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offs_4" title="Slice index offset [0-3] (field &quot;off2&quot;)">&lt;offs&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off2);
constant integer esize = 32;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_doubleword"/>64-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td colspan="3" class="lr">Pg</td><td class="lr">0</td><td colspan="3" class="lr">ZAn</td><td class="lr">o1</td><td colspan="5" class="lr">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="5"/><td class="droppedname">Q</td><td/><td colspan="2"/><td colspan="3"/><td/><td colspan="3"/><td/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_z_p_rza_d"/><p class="asm-code">MOVA    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.D, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>/M, <a href="#sa_zan" title="ZA tile ZA0-ZA7 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.D[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offs_1" title="Slice index offset [0-1] (field &quot;o1&quot;)">&lt;offs&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(o1);
constant integer esize = 64;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_quadword"/>128-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td colspan="3" class="lr">Pg</td><td class="lr">0</td><td colspan="4" class="lr">ZAn</td><td colspan="5" class="lr">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="5"/><td class="droppedname">Q</td><td/><td colspan="2"/><td colspan="3"/><td/><td colspan="4"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_z_p_rza_q"/><p class="asm-code">MOVA    <a href="#sa_zd" title="Destination scalable vector register (field &quot;Zd&quot;)">&lt;Zd&gt;</a>.Q, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field &quot;Pg&quot;)">&lt;Pg&gt;</a>/M, <a href="#sa_zan_2" title="ZA tile ZA0-ZA15 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.Q[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offs_3" title="Slice index offset 0">&lt;offs&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = 0;
constant integer esize = 128;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
boolean vertical = V == '1';</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zd&gt;</td><td><a id="sa_zd"/>
        
          <p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pg&gt;</td><td><a id="sa_pg"/>
        
          <p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;ZAn&gt;</td><td><a id="sa_zan_1"/>
        
          
        
        
          <p class="aml">For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_zan_3"/>
        
          
        
        
          <p class="aml">For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_zan"/>
        
          
        
        
          <p class="aml">For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_zan_2"/>
        
          
        
        
          <p class="aml">For the 128-bit variant: is the name of the ZA tile ZA0-ZA15 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;HV&gt;</td><td><a id="sa_hv"/>
        <p>Is the horizontal or vertical slice indicator, 
      encoded in
      <q>V</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">V</th>
                <th class="symbol">&lt;HV&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">V</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ws&gt;</td><td><a id="sa_ws"/>
        
          <p class="aml">Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offs&gt;</td><td><a id="sa_offs"/>
        
          
        
        
          <p class="aml">For the 8-bit variant: is the slice index offset, in the range 0 to 15, encoded in the "off4" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_offs_2"/>
        
          
        
        
          <p class="aml">For the 16-bit variant: is the slice index offset, in the range 0 to 7, encoded in the "off3" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_offs_4"/>
        
          
        
        
          <p class="aml">For the 32-bit variant: is the slice index offset, in the range 0 to 3, encoded in the "off2" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_offs_1"/>
        
          
        
        
          <p class="aml">For the 64-bit variant: is the slice index offset, in the range 0 to 1, encoded in the "o1" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_offs_3"/>
        
          
        
        
          <p class="aml">For the 128-bit variant: is the slice index offset 0.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer dim = VL DIV esize;
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
bits(32) index = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[s, 32];
integer  slice = (<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(index) + offset) MOD dim;
bits(VL) operand = <a href="shared_pseudocode.html#impl-aarch64.ZAslice.read.5" title="accessor: bits(width) ZAslice[integer tile, integer esize, boolean vertical, integer slice, integer width]">ZAslice</a>[n, esize, vertical, slice, VL];
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];

for e = 0 to dim-1
    bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
    if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
        <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element;

<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p>
    </div>
  <h3>Operational information</h3><p class="aml">If PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
                  The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
                </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
                  The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
                </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
